The present invention relates generally to the fabrication of integrated circuits containing both bipolar transistors and complementary metal-oxide-silicon (CMOS) transistors in a silicon wafer. More particularly, the present invention is directed to such a fabrication process wherein multiple bipolar transistors having different current gains and voltage breakdowns are produced by out-diffusing impurities from surface conductors of the integrated circuit into the silicon wafer to form the transistor emitters.
In the fabrication of static random access memories (SRAMs) as well as various other types of integrated circuits, it is known construct both P-channel and N-channel MOS transistors in a silicon wafer and to electrically isolate these transistors by the use of N-wells and P-wells, respectively. CMOS integrated circuits offer a more powerful circuit operation than either N-channel or P-channel circuits alone. This factor, combined with the lower power consumption and increased speed, has made CMOS the favored technology for the manufacture of microprocessors and memory devices. It is also well known to construct bipolar transistors in these integrated circuits in order to provide added circuit flexibility and current drive capability to these integrated circuits.
Earlier processes used for manufacturing these BiCMOS integrated circuits utilized separate and dedicated photoresist masking steps to form CMOS transistors on the one hand and the bipolar transistors on the other hand in order to provide the necessary processing isolation required in defining, doping, and making electrical connections to these different types of transistors. Typically, the areas of the silicon wafer in which the CMOS transistors were formed were subjected to a specific series of photolithographic masking and etching steps using photoresist masks to implant and then drive in dopant impurities into the CMOS transistor regions. Another completely different series of photolithographic masking and etching steps were then used for masking the area of the silicon wafer in which the bipolar transistor regions were formed using ion implantation and drive in diffusion processes well known in the art.
In order to reduce the number of processing steps required in the above prior art BiCMOS process, there has been developed a new and improved BiCMOS process wherein the bipolar transistors formed in the silicon wafer do not require dedicated photoresist masking and etching processes. This feature in turn thereby significantly reduces the total number of individual process steps and reticles required in the overall integrated circuit process flow. This new and improved process is disclosed and claimed in U.S. Pat. No. 4,987,089 issued to Ceredig Roberts, assigned to the present assignee and incorporated herein by reference.
The general purpose and principal object of the present invention is to provide still further new and useful improvements in the art of BiCMOS circuit fabrication and with respect to the novel process of U.S. Pat. No. 4,987,089. These improvements as disclosed and claimed herein serve to even further reduce the number of process steps and reticles required in the BiCMOS SRAM process flow for manufacturing these integrated circuits.
Another object of this invention is to provide a new and improved BiCMOS process of the type described which produces a maximum number of different transistor types, both MOS and bipolar, using the minimum number of individual integrated circuit fabrication steps.
Another object of this invention is to provide a new and improved BiCMOS process of the type described which operates to reduce manufacturing costs and enhance process yields.
Another object of this invention is to provide a new and improved BiCMOS process of the type described which operates to increase integrated circuit packing density.
Another object of this invention is to provide a new and improved BiCMOS process of the type described which is characterized by increased circuit design flexibility by offering three different bipolar transistor types having different gains and different voltage breakdown characteristics.
Another object of this invention is to provide a new and improved BiCMOS integrated circuit having improved bipolar transistor emitter connections.
A novel feature of this invention is the provision of a BiCMOS integrated circuit fabricated using a minimum number of wafer processing steps and yet offering the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and each of which is characterized by a different current gain and a different breakdown voltage.
Another feature of this invention is the provision of a differential silicon dioxide/silicon nitride masking process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein the P-type wells and the N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set.
To achieve the above purpose, objects, and novel features, the present BiCMOS integrated circuit fabrication process includes the steps of: forming first and second levels of polycrystalline silicon (polysilicon) on the surface of a silicon substrate and utilizing the first polysilicon level to electrically connect to an MOS transistor within the substrate (epitaxial layer) forming a bipolar transistor base region in the substrate; connecting the second level of polysilicon to the transistor base region; and out-diffusing impurities from the second level of polysilicon into the base region to thereby form the bipolar transistor emitter region, whereby separate ion implantation and drive-in diffusion steps to form the emitter region are eliminated.
In accordance with a preferred BiCMOS integrated circuit embodiment of the invention as a free-standing article of commerce and commensurate in scope with the broad article claims filed herein, there is provided a BiCMOS integrated circuit of the type having a first level of polysilicon connected to an MOS transistor in one region of a silicon substrate and a bipolar transistor formed in another region of the substrate. This embodiment is characterized in that the bipolar transistor emitter region is formed by connecting a second level of polysilicon to the bipolar transistor base region and out-diffusing impurities from second level of polysilicon to thereby convert the conductivity of the base region and form the transistor emitter region.
In accordance with the more specific process and device claims according to the present invention, there is provided a new and improved BiCMOS integrated circuit wherein initially N-type and P-type buried layers are formed in a silicon substrate and thereafter an epitaxial layer is formed on the surface of these N-type and P-type buried layers. Then, N-type and P-type wells are formed in the epitaxial layer using conventional CMOS processing technology. Net, the P-channel and N-channel MOS transistors are formed in adjacent N-wells and P-wells utilizing a first level of polysilicon as the MOS transistor gate electrodes. Then, using both first and second levels of polysilicon and further using a metal contact in combination with ion implantation, first, second, and third bipolar transistors are formed in adjacent regions of the epitaxial layer and in separate P-type or N-type wells therein. The emitter of the first bipolar transistor is formed by out-diffusion of impurities from a first level of polysilicon, whereas the emitter of the second bipolar transistor is formed by out-diffusion of impurities from the second level of polysilicon. The third bipolar transistor is formed by first implanting ions to form the emitter region within the previously formed base region of the transistor, and ohmic contact is made to the emitter via a metal connection. Each of the above three (3) bipolar transistors has a different current gain and a different breakdown voltage and thus affords the integrated circuit designer with a high degree of circuit design flexibility when making interconnections in the BiCMOS integrated circuitry thus formed.
The above brief summary of the invention, together with its stated objects, various related advantages and novel features, will become more readily apparent with reference to the following description of the accompanying drawings.